{"dataType":"CVE_RECORD","dataVersion":"5.2","cveMetadata":{"cveId":"CVE-2023-53043","assignerOrgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","state":"PUBLISHED","assignerShortName":"Linux","dateReserved":"2025-04-16T07:18:43.827Z","datePublished":"2025-05-02T15:55:00.724Z","dateUpdated":"2026-08-05T09:12:30.526Z"},"containers":{"cna":{"providerMetadata":{"orgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","shortName":"Linux","dateUpdated":"2026-08-05T09:12:30.526Z"},"descriptions":[{"lang":"en","value":"In the Linux kernel, the following vulnerability has been resolved:\n\narm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent\n\nIf the controller is not marked as cache coherent, then kernel will\ntry to ensure coherency during dma-ops and that may cause data corruption.\nSo, mark the PCIe node as dma-coherent as the devices on PCIe bus are\ncache coherent."}],"metrics":[{"cvssV3_1":{"version":"3.1","vectorString":"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H","baseScore":7.8,"baseSeverity":"HIGH"},"scenarios":[{"lang":"en","value":"AV:L - The missing dma-coherent property is on the SC7280 PCIe host; endpoints (notably built-in NVMe on Chromebooks/IDP) inherit that DT coherency via pci_dma_configure, and the bug is exercised by local block/filesystem I/O, not by network or adjacent-link protocols.\nAC:L - The controller is systematically treated as non-coherent on every DMA map/alloc on affected boards; a local process can reliably drive NVMe I/O and cache pressure to surface the incoherency, with no race or external precondition outside attacker influence.\nPR:L - Any unprivileged local user can generate PCIe/NVMe DMA traffic through ordinary file reads and writes on the root or data volume; no capability or real-root privilege is required.\nUI:N - Exploitation needs only the attacker’s own I/O; no separate victim action such as mounting a crafted image or plugging a device is required.\nS:U - Impact is confined to kernel-managed DMA buffers for the PCIe/NVMe device under the existing IOMMU mapping; this is a cache-coherency attribute mismatch, not an IOMMU/DMA-boundary bypass or VM escape.\nC:H - Treating a coherent device as non-coherent causes post-DMA cache invalidates that can discard device-written lines so the CPU returns prior page contents (freed kernel/other-process memory) as file data, and the device may snoop stale cached data into completions and payloads.\nI:H - Stale cache contents can be what the NVMe device DMA-writes to storage or what corrupted submission-queue commands encode, corrupting file data and filesystem metadata, and the driver acts on malformed completion-queue entries it believes the controller wrote.\nA:H - The same class of bug corrupts NVMe submission/completion queues (invalid tags, probe/I/O failures), and incoherent DMA leads to I/O timeouts, controller resets, hangs, and kernel crashes on the primary storage path."}]}],"affected":[{"product":"Linux","vendor":"Linux","defaultStatus":"unaffected","repo":"https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git","programFiles":["arch/arm64/boot/dts/qcom/sc7280.dtsi"],"versions":[{"version":"92e0ee9f83b3bc1d5644b1dc36eae730d1e8694d","lessThan":"267b899375bf38944d915c9654d6eb434edad0ce","status":"affected","versionType":"git"},{"version":"92e0ee9f83b3bc1d5644b1dc36eae730d1e8694d","lessThan":"e43bba938e2c9104bb4f8bc417ac4d7bb29755e1","status":"affected","versionType":"git"},{"version":"92e0ee9f83b3bc1d5644b1dc36eae730d1e8694d","lessThan":"8a63441e83724fee1ef3fd37b237d40d90780766","status":"affected","versionType":"git"}]},{"product":"Linux","vendor":"Linux","defaultStatus":"affected","repo":"https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git","programFiles":["arch/arm64/boot/dts/qcom/sc7280.dtsi"],"versions":[{"version":"5.16","status":"affected"},{"version":"0","lessThan":"5.16","status":"unaffected","versionType":"semver"},{"version":"6.1.22","lessThanOrEqual":"6.1.*","status":"unaffected","versionType":"semver"},{"version":"6.2.9","lessThanOrEqual":"6.2.*","status":"unaffected","versionType":"semver"},{"version":"6.3","lessThanOrEqual":"*","status":"unaffected","versionType":"original_commit_for_fix"}]}],"cpeApplicability":[{"nodes":[{"operator":"OR","negate":false,"cpeMatch":[{"vulnerable":true,"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionStartIncluding":"5.16","versionEndExcluding":"6.1.22"},{"vulnerable":true,"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionStartIncluding":"5.16","versionEndExcluding":"6.2.9"},{"vulnerable":true,"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionStartIncluding":"5.16","versionEndExcluding":"6.3"}]}]}],"references":[{"url":"https://git.kernel.org/stable/c/267b899375bf38944d915c9654d6eb434edad0ce"},{"url":"https://git.kernel.org/stable/c/e43bba938e2c9104bb4f8bc417ac4d7bb29755e1"},{"url":"https://git.kernel.org/stable/c/8a63441e83724fee1ef3fd37b237d40d90780766"}],"title":"arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent","x_generator":{"engine":"bippy-1.2.0"}}}}